1. Field of the Invention
The invention relates to a sigma-delta converter for converting a digital input signal into an analog output signal.
2. Description of the Related Art
In digital to analog converters, as employed in digital radio communication reception devices for example, a digital input signal with 2N signal states and a fixed sampling frequency fa is usually transposed into an analog signal which should match the digital signal as well as possible in the frequency range −fa/2 to +fa/2.
In the case of high bit widths N in particular, the quantity of signal states to be implemented by analog circuit technology represents a fundamental problem since the 2N signal states are more and more difficult to discriminate from the quantization noise as their quantity increases. Consequently, the digital signal is interpolated by digital filters and what are referred to as sigma-delta modulators are employed which substantially reduce the bit width of the digital signal in the case of an increased sampling frequency and transform the accordingly increased quantization noise into previously unused frequency ranges. Structures of sigma-delta modulators which achieve shaping of the noise signal like that by higher-order IIR filters (Infinite Impulse Response filters) are particularly efficient in this respect. Digital to analog converters are connected on the outgoing circuit side of the sigma-delta modulators which convert the digital output signal of the sigma-delta modulators into an analog signal. Together, sigma-delta modulators and digital to analog converters produce what is referred to as the sigma-delta converter.
There are two approaches to achieving noise shaping in the case of sigma-delta modulators.
According to the first approach, higher-order feedback loops are employed which allow a reduction of the number of stages to up to two signal states. A disadvantageous effect is that the noise shaping results in possible instabilities in the case of high input signals with effect from the 3rd order.
According to the second approach, first-order and/or second-order cascade-connected structures are employed which are multi-stage and accordingly display stable operational behavior.
A detailed depiction of the structure and mode of functioning of sigma-delta modulators is given by S. R. Norsworthy, R. Schreier and G. Temes: “Delta-Sigma Converters, Theorie, Design und Simulation”, IEEE Press 1997, ISBN 0-7803-1045-4.
A specific cascade-connected structure of a sigma-delta modulator is described in DE 199 37 246. This cascade-connected structure firstly reduces the quantity of signal states and secondly largely guarantees stability even in the case of higher-order sigma-delta modulators.
Sigma-delta converters, where the quantity of signal states has been reduced to two, offer fundamental advantages for implementing the digital to analog converter. Variations in the signal amplitude or a possible direct voltage component in the signal do not affect the linearity of the analog output signal. A disadvantage, however, is the necessary high oversampling factor (the ratio of the useful bandwidth to the sampling rate of the sigma-delta converter) onto which the baseband signal has to be interpolated so that a certain signal-to-noise ratio can be ensured in the useful band.
If multi-stage sigma-delta converters are used in place of two-stage ones, then substantially smaller oversampling factors can be used in theory. A large number of quantization stages are typically required for this which must all be identically high so that the quantization noise is optimized. As described in “Delta-Sigma-Data-Converters, Theorie, Design and Simulation”, 1996, by S. R. Norsworthy, R. Schreier and G. Temes for example, this problem is solved by employing a large number of two-stage digital to analog converters. A specific scrambling algorithm after the actual sigma-delta converter ensures that the data stream of each individual sigma-delta converter is noise-shaped and causes little interference in the useful signal band (noise shaped element usage). The stability of the algorithm is not ensured with effect from the 2nd order. Its cost is relatively high due to the vector quantizer used in this case. Furthermore, the structure of this scrambling algorithm is not linear and it generates feedback, which stands in the way of direct paralleling.